Hitherto, in order to store various data in a semiconductor integrated circuit, a semiconductor memory circuit such as an SRAM (static random access memory) and a DRAM (dynamic random access memory) have been used.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2006-331568    [Non patent Document 1] Kevin Zhang, Ken Hose, Vivek De, and Borys Senyk “The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18 μm Technologies” Symposium on VLS1 Circuits Digest of Technical Papers, PP 226-227, 2000.    [Non patent Document 2] J. Davis, D. Plass, P. Bunce, Y. Chan, A. Pelella, R. Joshi, A. Chen, W. Huott, T. Knips, P. Patel, K. Lo, and E. Fluhr “A 5.6 GHz 64 kB Dual-Read Data Cache for the POWER6 Processor” IEEE International Solid-State Circuits Conference, 2006.
The semiconductor memory circuit has adopted a dynamic circuit in which a single p-type MOS transistor connects to a single bit line. The adoption of the dynamic circuit may reduce the load capacity of the bit line more than a static circuit because only one transistor connects to the bit line and thus may increase the operation speed. Also, since the dynamic circuit may be configured by a lower number of transistors, which may reduce the circuit area.
The semiconductor memory circuit in the past having a column selection circuit in the local bit line as illustrated in FIG. 6A has a lower discharge speed of the local bit line, resulting in a decrease in reading speed.
As illustrated in FIGS. 6A and 6B and FIG. 7, a CELL (a memory cell) is selected by the WL (word line) and the local bit line 71, and the addition of a local readinq circuit 201 configured by two or more transistors such as an inverter 205, column mux 204 and a NAND 202 to the end of the local bit line 71 may reduce the discharge speed of the local bit line. As a result, the reading speed of the semiconductor memory circuit may decrease.
As illustrated in FIG. 6A and FIG. 6B, the column selection in global reading instead of column selection in local reading using a local read circuit 201 (hereinafter also referred to as “local region”) may possibly include charging/discharging with column mux 203 in the global bit line 111 for all columns, which may increase the power consumption. The local read circuit 201 includes MUX AND “L2” OUTPUT LATCH, and “LS” LATCH.
In FIG. 8, the reading speed is increased by a pre-discharge dynamic circuit having the end of the local bit line 71 connecting to one p-type transistor. (Refer to (A) in FIG. 8). However, since, as described above, the column selection is not performed in the local region, the power consumption disadvantageously increases. For example, the addition of a column selection circuit to the circuit illustrated in FIG. 8 may also necessarily increase the number of transistors. Both of a pre-discharge signal (PREN-A) and column selection signal may be required to input to the local region, which may also require the wiring area there for. For these reasons, building the column selection circuit into the circuit illustrated in FIG. 8 increases the size of circuit. FIGS. 6A and 6B to FIG. 8 are diagrams of circuit configurations in the past.